Condition Logic
The condition logic supports two types of tests: comparisons with zero and
comparisons between two unsigned numbers.
A trick is used to detect if a value is equal to zero. Instead of having
dedicated zerodetect logic (which would normally be implemented as a
wideinput NOR gate), the carry chain of the ALU is used. If the value
under test is negated, then the carry output from the ALU will be high if
and only if the input value is exactly zero.
Comparisons with zero
In this mode, the A field will indicate a memory location to test and the B
field will specify a jump address to take if the condition is true. The ALU
should be set up to negate the A operand in order to test for zero. If the
A operand is zero, the carry out from the ALU will be 1.
Instruction set up for comparison with zero:
 CEN = 0
 CINV = 1
 COM = 1
 BEN = 0
 A has address of data to test
 B has jump address
Comparison between two unsigned arguments
First, a subtraction instruction is issued with the two arguments to
compare. In other words, compute X  Y. The result should be saved back to
X in order for the second instruction to test it for zero.
Instruction set up for subtraction part:
 B points to the left side argument X
 A points to the right side argument Y
 CEN = 0
 CINV = 1
 COM = 1
 BEN = 1
 WRB = 1
Second, issue the conditional instruction with the subtraction result as the
A operand to the ALU.
Instruction setup for conditional jump part:
 A points to X (which was written to by the previous instruction).
 B has the jump address.
 CEN = 0
 CINV = 1
 COM = 1
 BEN = 0
Condition Codes
Here is a summary of the condition codes. Key:
 N is bit 7 of the A argument of the ALU.
 Z is the carryout value of the ALU (which is the input to the carry
flag).
 C is the carry flag (the carryout of the ALU from the previous
instruction).
 A is A operand to the ALU
 X and Y are arguments to an immediately preceding subtraction
instruction (performing X  Y). The result of this instruction should be
presented to the A argument of the ALU for the zero test.
The logical design of the condition decoder is as follows. cc0  cc3 are
the 4 bits from the cc field of the instruction.
It is implemented with 5 relays as follows. The carry flag provides
both inverting and noninverting outputs, so c_l comes directly from it.
